Tensile strained silicon (s-Si) enhances electron mobility by lifting the conduction band degeneracies, reducing carrier scattering and increasing the population of carriers in sub-bands with lower transverse effective mass. Channel engineering using Si or s-Si for an nFET and compressive strained SiGe for a pFET is a viable option for realizing small geometry devices while meeting performance targets. Multiple epitaxial deposition approaches might potentially be used for fabricating nFETs and pFETs, however the design rules and epitaxial non-idealities such as corner rounding, thickness and surface control limit the heterogeneous integration of Si and SiGe.